1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly, to a dynamic semiconductor memory device operable in a refresh mode in which a refresh (restoring) of a stored data is performed. More particularly, the present invention relates to a configuration for refresh control in a dynamic semiconductor memory device.
2. Description of the Background Art
In a dynamic type semiconductor memory device (DRAM), a memory cell is constructed of one transistor and one capacitor. Information is stored in a memory capacitor in an electrical charge form. When the accumulated charge in the memory cell capacitor is lost due to leakage current or the like, a stored data therein is destroyed. Therefore, in order to prevent destruction of a stored data, a refresh operation is performed to restore a stored data in a memory cell in a prescribed period. A refresh mode includes an auto-refresh mode in which a refresh instruction is externally supplied to perform refresh of memory cell data, and a self-refresh mode in which refresh timing is automatically determined internally to perform a refresh operation.
In any of the auto-refresh mode and the self-refresh mode, a refresh address specifying a memory cell (a memory cell row) to be refreshed is generated from an internally provided counter.
FIG. 63 is a chart representing an application sequence of external signals of a conventional DRAM in the auto-refresh mode. The DRAM referred in FIG. 63 takes in an externally applied command CMD in synchronization with a clock signal CLK, to perform an operation according to the taken in command.
First, in a clock cycle #1, a precharge command PRG is supplied. The precharge command PRG is taken into the DRAM at the rise of the external clock signal CLK and an internal precharge operation is performed (in this operation, the memory device is restored to an initial state).
In a next clock cycle #2, a no-operation command NOP is supplied as a command CMD. This is because when the internal circuitry is restored to an initial state by supplying the precharge command PRG, a so-called RAS precharge period is ensured
In a clock cycle #3, an auto-refresh command ARF is supplied. The auto-refresh command ARF is taken into the memory device at a rising edge of the external clock signal CLK, and a refresh activation signal RFACT is maintained at H level internally for a prescribed period to perform refresh of memory cell data.
In a clock cycle #4, a no-operation command NOP is again supplied. This is done to ensure an activation period of the refresh activation signal RFACT and the precharge period following the activation period.
Subsequently, in a clock cycle #5, auto-refresh command ARF is again supplied. A refresh operation of memory cell data is again performed according to a refresh address generated internally following the auto-refresh command ARF. The auto-refresh command ARF is repeatedly supplied successively a prescribed number of times. A certain period is used as a refresh period and in the remaining period, data access is performed according to another command CMD so as to realize efficient data access.
FIG. 64A is a block diagram schematically showing a configuration of a refresh address generating section. In FIG. 64A, the refresh address generating section includes: an address buffer 900 taking in an address signal AD supplied externally in a normal operating mode; a refresh address generating circuit 901 generating a refresh address specifying a memory cell to be refreshed; a multiplexer (MUX) 901 selecting one of an address signal from the address buffer 900 and the refresh address from the refresh address generating circuit 901 according to a select signal SEL to generate an internal address signal ADin; and a decoder 903 decoding an internal address signal ADin from multiplexer 902 to drive a word line WL provided corresponding to an addressed row to a selected state.
The selection signal SEL is activated when auto-refresh command ARF or self-refresh command SRF instructing the self-refresh mode is supplied. The multiplexer 902 selects a refresh address from the refresh address generating circuit 901 in a refresh mode (including the auto-refresh mode and the self-refresh mode) in response to activation of the selection signal SEL. The decoder 903 is activated in response to activation of a row-related activation signal RACT and decodes an internal address signal ADin to drive a word line on a selected row to a selected state when activated. The address buffer 900 is activated in accordance with a command supplied in the normal operating mode and takes in and latch an address signal supplied externally to generate an internal address signal.
FIG. 64B is a waveform diagram representing operations in the refresh mode. When auto-refresh command ARF is supplied as a command CMD, the auto-refresh command ARF is internally taken in at the rise of the clock signal CLK (see FIG. 63) and a refresh activation signal RFACT is activated in accordance with the taken-in auto-refresh command ARF and the selection signal SEL is activated in response to the refresh activation signal RFACT. When the selection signal SEL is activated, the multiplexer 902 selects the refresh address from refresh address generating circuit 901 to generate an internal address signal ADin. After the internal address signal ADin becomes definite, decoder 903 activated by the row-related activation signal RACT performs a decode operation to drive a word line WL corresponding to an addressed row to a selected state.
Therefore, when an auto-refresh command ARF is supplied, a to-be-selected word line WL is driven to a selected state after elapse of time ta from the rise of a clock signal CLK or in a time tb after the row-related activation signal RACT is activated. This is because a command supplied externally is taken in at the rise of the clock signal CLK and then, an internal operation instructing signal is generated to start an internal operation.
On the other hand, when a self-refresh command SRF is supplied, selection signal SEL and refresh activation signal RFACT are activated in response to the self-refresh command SRF. The selection signal SEL maintains an active state at H level during the self-refresh mode. A row-related activation signal RACT is activated by a refresh request generated periodically from a refresh timer included in refresh address generating circuit 901. In the self-refresh mode, multiplexer 902 already selects a refresh address from refresh address generating circuit 901 according to selection signal SEL. When a refresh request is generated, an internal address signal ADin is in the definite state; therefore, decoder 903 performs a decode operation in response to a row-related activation signal RACT to drive a selected word line WL to a selected state.
In the self-refresh mode, it is necessary to take a time tc to drive a word line WL to a selected state after activation of row-related activation signal RACT, wherein times tb and tc are equal to each other. In the auto-refresh mode, decoder 903 is required to be activated after selection signal SEL is activated, and an internal address signal ADin becomes definite, and therefore timing adjustment becomes more complex than in the self-refresh mode, leading to a problem that a row-related control signal has to be activated at different activation timings between the self-refresh mode and the auto-refresh mode. In this case, it may be possibly considered that selection signal SEL is selectively activated by a refresh request in the self-refresh mode. When selection signal SEL is driven to an active state in response to a refresh request in the self-refresh mode, however, selection signal SEL has to be charged and discharged, to increase current consumed in the self-refresh mode in which a current consumption is required to be as small as possible.
Further, Japanese Patent Laying-Open No. 11-339174 discloses a technique that in order to advance internal operation start timing, a row address signal externally supplied is taken in asynchronously with clock signal CLK to supply the row address signal to a decoder or to perform a decode operation prior to application of a command.
In this case, however, a command CMD in the normal operating mode is taken in internally in synchronization with clock signal CLK to perform an internal operation. That is, an internal address signal is generated utilizing a set-up time of a command to perform spare determination or the like. Therefore, an auto-refresh command ARF is taken internally at a rise of clock signal CLK, and selection signal SEL is activated in synchronization with the clock signal CLK. Accordingly, in this prior art technique, in the auto-refresh mode, definite timing of an internal address signal ADin is determined by clock signal CLK and an internal operation start timing is delayed in the auto-refresh mode compared with that in the normal operating mode. That is, when the auto-refresh command is supplied externally, operation starting timing of the internal circuitry is different in application of a command in the normal operating mode (a Row ACT command) and in application of auto-refresh command. Further, a period of an auto-refresh is made longer, thereby increasing a waiting period in a normal access.
It is required to make an internal operation (a row selecting operation) start timing different between the auto-refresh command and commands applied in the other normal modes, leading to complexity in circuit configuration. This applies to a case where a timing margin of an address signal is different for the self-refresh mode and for the auto-refresh mode.
In the self-refresh mode, what is required is only to hold a stored data in a memory cell. In applications such as a portable equipment, an amount of data to be held is limited. Therefore, when a refresh region is limited to a part of a whole address region, a number of times of refresh can be reduced. More specifically, since a refresh cycle of a memory cell is of a prescribed time period, when a refresh region is set to a half of a whole address region, for examples, the number of times of refresh can be reduced by a factor of 2, thereby enabling a current consumed in the self-refresh mode to decrease correspondingly. On the other hand, in the auto-refresh mode, whole the address region is refreshed according to the auto-refresh command supplied externally. This is to prevent a data under processing from vanishing. Accordingly, since a refresh region is limited in the self-refresh mode, there causes a necessity to change a configuration for generating a refresh address according to which mode of the auto-refresh mode and the self-refresh mode is designated.
Further, when a refresh address region is restricted, if a redundancy circuit for replacing a defective row with a spare row is provided, redundancy replacement has to be performed efficiently and correctly. Conventionally, however, no disclosure is provided on circuit configuration with which a refresh address region is changed with ease between the auto-refresh mode and the self-refresh mode and a current consumption is reduced in the self-refresh mode. Especially, when a configuration of a control circuit for the address modification and reduction of current consumption increases in complexity and in addition, a current consumption in the self-refresh mode is caused, a lifetime of a battery in a portable equipment is shortened and a normal operation is adversely affected.
It is an object of the present invention to provide a dynamic semiconductor memory device capable of performing self-refresh and auto-refresh with ease, stability and a reduced current consumption.
It is another object of the present invention to provide a dynamic semiconductor memory device capable of processing a row access command and an auto-refresh command at the same timing in performing an internal operation.
It is still another object of the present invention to provide a dynamic semiconductor memory device capable of reducing a current consumption in the refresh mode much more.
A semiconductor memory device according to an aspect of the present invention includes: a refresh address generating circuit for generating a refresh address specifying a memory cell to be refreshed in a refresh mode; an address circuit for generating an internal address based on the refresh address in asynchronization with a clock signal; and a refresh control circuit taking in a refresh instruction supplied externally in synchronization with a clock signal and generating a refresh control signal to perform refresh of a memory cell specified by the internal address according to the taken in refresh instruction.
A semiconductor memory circuit according to a second aspect of the present invention includes: a plurality of memory sub-blocks each having a plurality of normal memory cells disposed in a matrix of rows and columns. The plurality of memory sub-blocks are arranged in alignment in a row direction.
A semiconductor memory device according to the second aspect of the present invention further includes: a plurality of normal sub-word lines, provided corresponding to the respective rows in each of the plurality of memory sub-blocks, each connecting to the normal memory cells on a corresponding row; a plurality of normal main word lines, disposed extending in a row direction in common to the plurality of memory sub-blocks, each provided corresponding to a prescribed number of normal sub-word lines in each of the plurality of memory sub-blocks; and a plurality of spare memory cells disposed aligned on at least one row in each of the plurality of memory sub-blocks. The plurality of spare memory cells are disposed aligned in a column direction with normal memory cells in a corresponding memory sub-block.
A semiconductor memory device according to the second aspect of the present invention further includes: a plurality of spare sub-word lines, provided corresponding to spare memory cell rows in the plurality of memory sub-blocks, each connecting to spare memory cells on a corresponding row; at least one spare main word line, disposed extending in the row direction in common to the plurality of memory sub-blocks, provided corresponding to a prescribed number of spare sub-word lines in each of the plurality of memory sub-blocks; and a repairing control circuit for storing a defect address indicating a position of a defective normal memory cell for replacing a normal sub-word line on the defective row with a spare sub-word line in a corresponding memory sub-block when a row including a defective normal memory cell is specified. At least, in a data holding mode, defect repairing is performed on a sub-word line basis.
A semiconductor memory device according to a third aspect of the present invention includes: a circuit for storing bit information indicating a storage capacity of a memory array; and a refresh size setting circuit for setting a size of rows to be refreshed of a memory array according to the bit information in a refresh mode in which a stored data in a memory array is refreshed.
When a refresh instruction is applied externally, a refresh address is taken in asynchronously with a clock signal to generate an internal address, and the internal address can be generated utilizing a set-up time for a refresh command, which enables advancement in start timing for internal refresh operation. Further, by taking in an address signal asynchronously with the clock signal, similarly to other commands, for the auto-refresh command and a normal row active command, the address signals can be internally decoded to start internal operations at the same timing, and a circuit configuration can be made common to any external command to simplify a circuit configuration. Activation timing of an internal refresh address signal can be the same in both of the self-refresh mode and the auto-refresh mode, thereby enabling simplification of circuit configuration for refresh through commonization thereof.
Further, by enabling repairing of a defective memory cell on a sub-word line basis, correct refreshing of a stored data can be ensured, even when a consumed current is reduced through activation of only a prescribed number of sub-word lines in the data holding mode. Further, by setting a refresh row size adjustably according to a storage capacity, the number of sense amplifier operating concurrently can be optimized to stabilize a sense power supply voltage even when a value of decoupling capacitance of a sense power supply voltage line is small.